The present invention relates to a semiconductor device having body contacts and a method for fabricating the semiconductor device, more specifically to a semiconductor device which has a reduced gate capacitance and suppresses speed performance deterioration of the transistors, and a method for fabricating the semiconductor device.
Recently, as semiconductor devices are larger-scaled and more integrated, semiconductor integrated circuits are made to have higher performances and lower electric power consumption. It is proposed to use SOI (Silicon On Insulator) substrates. The SOI substrate is a substrate having a thin semiconductor layer formed on an insulation layer. The SOI substrate, which permits a device isolation film arriving at the insulation layer to fully isolate devices from each other, and also permits a dopant diffused layer formed in regions arriving at the insulation layer to much reduce junction leak current and junction capacitances. Thus, the SOI substrate is suitable for semiconductor devices requiring high speed operations. The devices formed on the semiconductor layer are isolated from the substrate by the insulation layer, with advantageous results of high α-ray resistance and latch-up resistance.
On the other hand, in a MOSFET using the SOI substrate, the potential of the body region floats, and potential changes in the body region affect the operation of the MOSFET. That is, secondary carriers, which are generated by impact ionization in the pinch-off region and are the same type as carriers in the channel region (holes in the NMOS and electrons in the PMOS) are accumulated in a lower region of the channel (the body region), which is electrically floated, and cause body potential changes (floating body effect). This floating body effect is a cause of device characteristic deviations, which makes margin design of a circuit difficult.
Various countermeasures to the floating body effect are proposed, but a method of providing an electrode in the body region so as to fix a potential is most secure and is generally used.
As one method of forming a contact to the body region, a region of a conduction type inverse to the source/drain region of the MOSFET (body contact region) is formed in the device region where the MOSFET is formed. The boundary between the body contact region and the source/drain region is covered with a gate electrode formed in a T-shape, L-shape or H-shape so as to isolate the device region and the body contact portion.
FIG. 30A shows a structure called the T-shape. One device region 100 is divided by a T-shaped gate electrode 108 in a source region 102, a drain region 104 and a body contact region 106. A device region below the gate electrode 108 (body region) is formed of a semiconductor layer of the same conduction type as the body contact region 106 and is electrically connected to the body contact region 106.
FIG. 30B shows a structure called the L-shape. One device region 100 is divided by an L-shaped gate electrode 108 in a source region 102 and a body contact region 108, and a drain region 104. A device region below a gate electrode 108 (body region) is formed of a semiconductor layer of the same conduction type as the body contact region 106 and electrically connected to the body contact region. Such structure is applicable to a semiconductor device which can set a source potential and a body potential at the same potential.
In these semiconductor devices, the gate electrodes 108 are extended to isolate the source region 102 or the drain region 104 from the body contact region 106. This is in consideration of salicide (self-aligned silicide) process. That is, in using salicide process, silicide film covers that of the device region 100 where the gate electrode 108, and a sidewall insulation film (not shown) formed on the side walls of the gate electrode 108 are not formed. Accordingly, unless the gate electrode 108 is formed so that the drain region is isolated from the body contact region 106, or the source region 102 and the drain region 104 are isolated from the body contact region 106, these regions are electrically connected to one another.
The gate electrode is thus extended, whereby the body contact region can be isolated from the drain region 104, or from the source region 102 and the drain region 104.
However, in the conventional semiconductor device shown in FIG. 30, the gate electrode is extended over the device region where the gate electrode does not play the role of the gate electrode with interposing the gate insulation film therebetween. A parasitic capacitance of this region is added to a gate capacitance of the MOSFET. That is, in the semiconductor device shown in FIG. 30A, when the T-shaped gate electrode 108 has the region at the longitudinal bar as the gate electrode 108 and the region at the lateral bar as a dummy electrode 108b, a parasitic capacitance Cp given by the dummy electrode 108b is connected parallelly with the MOSFET, and a gate capacitance is increased by the parasitic capacitance as shown in FIG. 31. The semiconductor device shown in FIG. 30B has the area of the dummy electrode 108b decreased, whereby the parasitic capacitance Cp can be decreased. The reduction of the parasitic capacitance Cp is not enough.
To implant ions in the source region 102 and the drain region 104, a lithography step for forming a mask pattern exposing the region 110 for the MOSFET to be formed in is necessary, and a mask pattern exposing the region 112 for the body contact to be formed in is necessary to implant ions in the body contact region 106. To secure disalignment margins in these lithography steps, as shown in FIG. 30 the ends of the patterns are positioned on the dummy electrode 108b. Accordingly, a width of the dummy electrode 108b must be set to be large enough for a disalignment margin, which adds much to a gate capacitance.
Thus, a semiconductor device having body contact regions has excessive additions to a gate capacitance and a junction capacitance, and the effect of parasitic capacitance reduction, which is a merit of using SOI substrates cannot be sufficiently used.
In the semiconductor devices shown in FIG. 30, a gate width of the MOSFET is defined by the gate electrode 108 on one side and is defined by the device region 100 on the other side. Accordingly, a gate width varies depending on the disalignment in the lithography step for forming the gate electrode 108.
On the other hand, as a device isolation technique which can control a insulation width and an insulation depth independently of each other, the so-called shallow trench isolation (STI) technique, in which a shallow trench is formed, and an insulation film is buried in the trench to form a device isolation film, is used. STI technique is superior to the conventional LOCOS in micronization, but has the problem that the channel width dependency of the electric characteristics, especially sub-threshold characteristics of MOSFET becomes higher (narrow channel effect). A main reason for this is that due to electric field concentration and disuniform impurity distribution taking place at the corners of the surface of the interface between the device isolation film and the device region, electric characteristics at these region differ from the intrinsic electric characteristics at the center of the channel. To solve this problem, the corners of the device region border are rounded, or etc. to thereby reduce the effect but insufficiently.